1. Field of the Invention
This invention relates to the field of decoding circuits for electrically erasable, read only memories (E.sup.2 PROM).
2. Prior Art
In field of MOS integrated circuits memories, memory cell sizes have been greatly reduced. Memory layouts have utilized memory cells arranged along row lines (word lines) in an array with row decoders disposed either along the ends of these lines or bisecting these lines. The decoders enable individual row lines to be accessed and when used in conjunction with column decoders, allow individual cells to be accessed from the memory.
Typically, these decoders have been used in conjunction with read only memory (ROM) or random access memory (RAM). One example of a prior art decoder may be found in U.S. Pat. No. 4,264,828 entitled "MOS Static Decoding Circuit" and assigned to the assigneee of the present invention.
Prior art decoding circuits have the disadvantage of incompatibility with electrically erasable, programmable read only memories (E.sup.2 PROM). E.sup.2 PROMs function much like ROMs, in that information may be permanently stored in the cells of the memory array. However, in an E.sup.2 PROM, the cells can be reprogrammed when subjected to a voltage signal of sufficient strength to change the state of the cell.
It is an object of the present to provide a decoder circuit which can be used with an E.sup.2 PROM. It is a further object of the present invention to provide a decoder which allows erasing of a single word line as well as the erasing of all the word lines.